1. Field of the Invention
The present invention relates to a method for adjusting a delay value of a signal path by inserting a delay gate, which is a standard cell of a semiconductor integrated circuit, into a signal path formed in the semiconductor integrated circuit. The invention also relates to the semiconductor integrated circuit, in which the delay value of the signal path is adjusted with the same method.
2. Description of the Related Art
Generally speaking, when change in a manufacturing process of a semiconductor integrated circuit causes transistor performance variation (hereinafter will be called the “process variation”), the delay value of each signal path is required to be adjusted to satisfy a predetermined value. Thus, when designing semiconductor integrated circuits, delay gates are commonly inserted into signal paths with small delay values, as a measurement against racing among latches.
The individual delay gates, which are standard cells of semiconductor integrated circuits, include two or more transistors in combination. More precisely, as shown in FIG. 8A through FIG. 8C, one or more inverters 10, each of which is a combination of a P-channel MOS (Metal Oxided Semiconductor) transistor 10p and an N-channel MOS transistor 10n, are connected, thereby forming a delay gate (see, for example, the following patent application 1 through 3).
The delay gate 1 of FIG. 8A is formed by five inverters 10 connected; the delay gate 2 of FIG. 8B is formed by four inverters 10 connected; the delay gate 3 of FIG. 8C is formed by three inverters 10 connected. Since the delay gates 1 and 3 of FIG. 8A and FIG. 8C, respectively, are formed by an odd number of inverters 10, they function as inverters. On the other hand, since the delay gate 2 of FIG. 8B is formed by an even number of inverters 10, it functions as a buffer.
In such common delay value adjusting methods using delay gates, the number of inverters connected, which form delay gates, is varied, or the gate lengths L of the transistors forming the delay gates are varied. In the former method, the greater the number of inverters connected, the greater the delay value realized. In the latter method, the greater the gate length L, the greater the delay value realized.
As a common procedure, the gate widths W of the transistors are changed, before the number of inverters connected is increased or before the gate lengths L of the transistors are changed, so as to adjust the delay value (see, for example, the following patent application 1). Generally speaking, the smaller the gate width W, the greater the delay value, whereas the greater the gate width W, the smaller the delay value. Therefore, first of all, the gate width W is firstly changed to adjust the delay value, and then, if it is still impossible to control the delay value of the delay gate to a desired value (that is, if the delay value exceeds a delay value adjustable range in which the delay value can be adjusted by changing the gate widths W of the transistors), the number of inverters connected and the lengths L of the transistors are changed, to adjust the delay value.
[Patent application 1] Japanese Patent Application Publication No. HEI 5-226619
[Patent application 2] Japanese Patent Application Publication No. HEI 5-226988
[Patent application 1] Japanese Patent Application Publication No. HEI 5-268015
However, the method in which the number of inverters is changed to adjust the delay value faces the following problem. If the delay value exceeds the range that can be adjusted by gate width W variation, the number of inverters connected is changed, so that the area (cell size, that is, the size of the delay gate) and metal wiring require changing.
Further, the method in which the gate lengths L of transistors are changed to adjust the delay value faces the following problem. If the delay value exceeds the range that can be adjusted by gate width W variation, some packaging rules necessitate change in cell size and in metal wiring. Furthermore, since the gate lengths L of the transistors are influenced by manufacturing variations, all the transistors preferably have the same gate length L, and it is thus undesirable that the delay value adjustment is performed by changing the gate length L.
In both of the previous delay value adjusting methods, if the delay value exceeds the range that can be adjusted by gate width W variation, the cell size and metal wiring must be changed, so that cell rearrangement and rewiring in high-order design (for example, layout design of standard cells including delay gates) are necessitated.